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Electronics

The WII6 board: an STM32U575 on Zephyr, an ESP32-S3 debug processor, Iridium Certus, and power and voltage monitoring on multiple buses.
The WII5 v2 main board. In WII6, the STM32 takes over control and wave processing from the ATmega2560 and Raspberry Pi.

The WII5 v2 main board. In WII6, the STM32 takes over control and wave processing from the ATmega2560 and Raspberry Pi.

The board

Role Part Purpose
Main processor STM32U575ZI ST’s ultra-low-power line, five serial ports, 786 kB SRAM for the wave maths, Zephyr support upstream
Debug processor ESP32-S3 on a XIAO socket WiFi, Bluetooth and a web server, powered down during deployment
Motion Sparton AHRS-M2 option proven on multiple WII5 deployments
Satellite RockBLOCK 9704, Iridium Certus about 100 kB a message, which is what lets the 2 Hz record travel
Position u-blox GNSS, NMEA position and time from a single receiver; a dual-antenna model is available for accurate heading near the poles
Temperature DS18B20 probes temperature measurements for the deployment
Power monitoring INA3221 and INA228 power and voltage measurements on multiple buses, plus battery monitoring
Storage one SD card full-rate records, 2 Hz records and wave results

Power monitoring

Power and voltage are measured on multiple buses, alongside battery monitoring, so a deployment can track energy use and the buoy’s health. Switched supplies let the firmware power down peripherals between jobs. The debug processor is powered down during deployment.

Duty cycle

Capture length and reporting interval are configurable. A fifteen-minute capture every two hours is one example; shorter captures, more frequent reports or daily reporting can be chosen to suit the deployment.

The power budget depends on time spent sampling, processing and sending data, as well as consumption between wake-ups. Sleep consumption matters most when the buoy spends long periods waiting for its next capture.

Firmware

Zephyr RTOS, built with west, with the wave maths as a library that builds and tests the same way on a workstation and on the processor. The bench image is a hardware test suite: each peripheral exercised on its own, with a shell for all of it and a JSON status frame once a second to the dashboard. The maths library, the card layout and the link protocol are documented in the engineering repository. Ask us for the documentation if you are planning an integration.